A charge pump circuit has been known that is used in a PLL (Phase Locked Loop) circuit generating a high clock frequency signal by multiplying an input clock frequency by a certain ratio (see, for example, Patent Document 1).
FIG. 1 is a configuration diagram illustrating a charge pump circuit disclosed in Patent Document 1. The charge pump circuit 1 includes a constant current source I1 connected with a potential VDD, and a constant current source 12 connected with a potential VSS. When a pMOS transistor MP1 turns on, the charge pump circuit 1 discharges a current to a loop filter at the following stage from the constant current source I1 via a node 2, and when a nMOS transistor MN1 turns on, the charge pump circuit 1 draws a current into the constant current source 12 from the loop filter at the following stage via the node 2. Also, the charge pump circuit 1 includes a pMOS transistor MP2 that operates inverse to an operation of the pMOS transistor MP1, and an nMOS transistor MN2 that operates inverse to an operation of the nMOS transistor MN1.
When one of the pMOS transistors MP1 and MP2 turns on, if the potential of the node N1 fluctuates, an error difference is generated in the constant current of the constant current source I1. Similarly, when one of the nMOS transistors MN1 and MN2 turns on, if the potential of the node N2 fluctuates, an error difference is generated in the constant current of the constant current source 12. To reduce these error differences, the charge pump circuit 1 makes the voltage of the node 2 and the voltage of the node 3 equivalent to each other by an amplifier 4, to have the node N1 always take a constant potential, and to have the node N2 always take a constant potential.